1. Field of the Invention
The embodiments of the invention generally relate electroplating features onto a semiconductor wafer and, more particularly, to an anti-fuse device structure and a circuit and method for electroplating as well as programming the anti-fuse device structure.
2. Description of the Related Art
An electroplating circuit typically includes an anode (i.e., a source of metal or alloy), a cathode (i.e., an item to be electroplated with the metal or alloy), an electroplating bath for holding an electroplating solution into which the anode and cathode are submerged and an external power supply connected to the anode and cathode to provide a current flow through the circuit. Specifically, the current flow and, thereby, electron flow will cause metal ions in the electroplating solution to lose their charge and plate onto the cathode. This current flow will further cause the anode to replenish the metal ions in the solution.
Electroplating (i.e., electrodeposition) is often used to form back end of the line (BEOL) features, such as wires, metal-insulator-metal devices, capacitors, etc., on a semiconductor wafer. For example, as described in “Damascene copper electroplating for chip interconnections” by Andricacos et. al, IBM Journal of Research and Development, Vol. 42, No. 5, 1998, various techniques can be used for forming a BEOL electroplated feature on a semiconductor wafer. One technique involves forming a seed layer (i.e., a thinly deposited conductive layer) on the wafer. Next, a mask is formed on the seed layer such that only that portion of the seed layer to be plated is exposed. A contact at the wafer edge conducts current through the seed layer during electroplating. Once the electroplating process is completed, the mask layer is removed, followed by removal of any exposed seed layer. Another technique involves forming a single-tier trench for metal lines only or a double-tier trench for metal lines and via holes. Next, a blanket barrier layer and blanket conductive seed layer are formed. A contact at the wafer edge conducts current through the seed layer during electroplating. Once the electroplating process is completed, a chemical-mechanical polishing (CMP) process is used to remove barrier material, seed material and electroplating material outside the trench.
As mentioned above, each of these techniques requires the use of a contacted seed layer (i.e., a thinly deposited conductive layer) to provide a current path from the power supply to the cathode (i.e., from the power supply to the area of the wafer that is to be electroplated). In the former technique, once the electroplating process is complete, additional process steps are required to remove the mask and any excess seed layer that was not electroplated. In the latter technique, once the electroplating process is complete, additional process steps are required to remove any excess seed layer, barrier layer and electroplated material outside the trench. These additional processing steps increase manufacturing costs and time. Consequently, there is a need in the art for an electroplating circuit and an electroplating method, which eliminates the need to use a seed layer and which minimizes the number of subsequent processing steps.